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AirStack BitStream 2.0.1

 

10 February 2026

 

The Deepwave team is excited to announce the release of AirStack BitStream 2.0.1. This is a minor release that has added a few new features and resolved some issues.

Please see the AirStack BitStream Programming Guide for full documentation. For older versions see previous release notes versions.

New Features

  • Per-Channel Buffer Size Parameters - The size of the Deepwave IP core DMA buffer related to each RX or TX channel can now be specified individually. This opens up the opportunity for even more application specific use of FPGA resources.

  • Resource Savings - A few percent less flip flops and LUTs are used by this version of the IP core.

Resolved Issues

  • TX Underflow Excess Data - Underflow no longer results in extra zero values samples being injected into the transmit datapath.

Potentially Breaking Changes

  • Only writeStream() calls that set the SOAPY_SDR_END_BURST flag will see an AXIS tlast cycle at the end of the data stream. Previously all write's ended with tlast.

Other Changes

Minor changes to be aware of:

  • Heater and blower enable PCB signals have been connected to the Deepwave IP core.
    • Top level constraints and ports were added.
  • If using the Vivado Upgrade IP flow, new ports on the IP core as well as new buffer sizing parameters are correctly reported in the output ip_upgrade.log.
  • The Deepwave IP core instance by default is configured to report latest version 2.0.1.
  • The internal structure of the Deepwave IP core has been reorganized so users can expect different messages from Vivado during the build process.
  • Documentation files included with AirStack BitStream have been renamed:
    • README.md is now programming_guide.md
    • UPGRADE.md is now release_notes.md
    • LICENSE.md is now bitstream_license.md